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[VHDL-FPGA-Verilog] da

Description: FIR滤波器利用串行DA算法实现16阶的，直接可用 ，用VHDL编程-Serial DA FIR filter algorithm using 16 bands, directly available, VHDL programming
Platform: | Size: 215040 | Author: 赵擎天 | Hits:

[VHDL-FPGA-Verilog] fir_PGA

Description: 一种基于verilog的fir滤波源码，并带matlab仿真源程序。-Based on the fir filter verilog source code and source code with matlab simulation.
Platform: | Size: 23552 | Author: 对称 | Hits:

[VHDL-FPGA-Verilog] dilbalu_fir7

Description: basic fir filtering in verilog fpga in vhdl
Platform: | Size: 142336 | Author: dileepkumar | Hits:

[VHDL-FPGA-Verilog] fir6dlms

Description: lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
Platform: | Size: 1024 | Author: lvchangbo | Hits:

[VHDL-FPGA-Verilog] fir

Description: vhdl code for fir filter
Platform: | Size: 1024 | Author: lekshmi | Hits:

[VHDL-FPGA-Verilog] fir

Description: this file contain a description in vhdl of a fir it contain three part well described to similate the behavior of the this type of filter
Platform: | Size: 11264 | Author: seif | Hits:

[VHDL-FPGA-Verilog] code

Description: it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm and the test bench of it.
Platform: | Size: 5120 | Author: syamprasad | Hits:

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

Description: ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project we compare the working of the three multiplier by implementing each of them separately in FIR filter.
Platform: | Size: 379904 | Author: phitoan | Hits:

[VHDL-FPGA-Verilog] ourdev_573514

Description: 高通滤波器的verilog实现，对初学者设计FIR有好处，分布式算法-Verilog implementation of high-pass filter, FIR design is good for beginners, distributed algorithm
Platform: | Size: 306176 | Author: 吴锦干 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
Platform: | Size: 470016 | Author: chenlan | Hits:

[VHDL-FPGA-Verilog] FIR_IP_lowpass

Description: 8阶FIR_IP的VHDL代码以及QuartusII的顶层文件-FIR_IP the VHDL code of order 8 and the top-level file QuartusII
Platform: | Size: 7205888 | Author: 李龙 | Hits:

[VHDL-FPGA-Verilog] fir(1)

Description: 基于fpga的fir数字滤波器的设计的用QUARTUS II 做的VHDL语言的源代码-The fir fpga based design of digital filters QUARTUS II to do with the source code for VHDL,
Platform: | Size: 988160 | Author: 郑晓坚 | Hits:

[VHDL-FPGA-Verilog] FIR_1

Description: FIR code in vhdl -FIR code in vhdl ----VVV
Platform: | Size: 75776 | Author: hr | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 采用vhdl语言 设计FIR滤波器，经调试好使，献给广大硬件开发的朋友参考学习-FIR filter design using vhdl language, so that upon commissioning, the development of friends dedicated to the general hardware reference learning
Platform: | Size: 8192 | Author: youlijun | Hits:

[VHDL-FPGA-Verilog] -VHDL

Description: 本报告分两部分： 1 由matlab计算FIR数字滤波器的滤波系数； 2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。 -FIR digital filters based on VHDL
Platform: | Size: 115712 | Author: | Hits:

[VHDL-FPGA-Verilog] Digital-Signal-Processing-with-FPGA

Description: FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
Platform: | Size: 10501120 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] FIR-LOOP-

Description: 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
Platform: | Size: 1024 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] fir-filter

Description: fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
Platform: | Size: 7241728 | Author: liu | Hits:

[VHDL-FPGA-Verilog] fir4

Description: 基于vhdl的长度为4的fir滤波器，经过官方软件认证-Based on the length of 4 vhdl fir filter, after the official software certification
Platform: | Size: 1024 | Author: 李亮 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: This FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit-This is FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit
Platform: | Size: 2669568 | Author: gurhans | Hits:
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